Wiring substrates and semiconductor devices having a silicon layer and a core substrate to which the silicon layer is joined are known. For example, it is assumed that, in wiring substrates having a silicon layer, the silicon layer functions as a base member through and on which through-holes and interconnections are formed but is not formed with any semiconductor circuits. On the other hand, semiconductor devices are such that semiconductor circuits are formed in the silicon layer of such wiring substrates.
In such wiring substrates and semiconductor devices, the silicon layer and the core substrate are electrically connected to each other by bumps such as solder bumps. To increase the reliability of the bump connections, the space between the silicon layer and the core substrate may be filled with an underfill resin so as to cover the bumps (for example, see JP-2005-072596-A).
However, since the silicon layer and the core substrate are electrically connected to each other by the bumps, due to the technical limitations in forming bump, in positioning the silicon layer and the core substrate with each other, in maintaining bump shapes, etc., it is difficult to increase the density of connections, and the number of connections is restricted. Furthermore, it is difficult to fill the space between the silicon layer and the core substrate with an underfill resin uniformly and completely. Still further, when the silicon layer is thin (e.g., 50 μm), it is difficult to handle the silicon layer at the time of bump connection. Similar problems arise when a glass layer is used instead of the silicon layer.